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INTEGRATED CIRCUITS
74ALVT16260 12-bit to 24-bit multiplexed D-type latches (3-State)
Product specification IC23 Data Handbook 1998 Jan 30
Philips Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
FEATURES
* ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in memory-interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction. Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is returned high. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The 74ALVT16260 is available in a 56-pin Shrink Small Outline Package (SSOP) and 56-pin Thin Shrink Small Outline Package (TSSOP).
* Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
* Distributed VCC and GND pin configuration minimizes high-speed
switching noise.
* Output capability (-32mA IOH, 64mA IOL). * Bus hold inputs eliminate the need for external pull-up resistors. * 5V I/O compatible * Live insertion/extraction permitted * Power-up 3-State * Power-up Reset
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay nAx to nBx nBx to nAx CL = 50 pF VI = 0 V or VCC VI/O = 0 V or 5.0 V Outputs disabled CONDITIONS Tamb = 25C; GND = 0V TYPICAL 2.5V 3.5 3.3 4 9 100 3.3V 2.8 2.6 4 9 80 ns pF pF A UNIT
Input capacitance Output capacitance Total supply current
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVT16260 DL 74ALVT16260 DGG NORTH AMERICA AV16260 DL AV16260 DGG DWG NUMBER SOT371-1 SOT364-1
1998 Jan 30
2
853-2046-18918
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
PIN DESCRIPTION
PIN NUMBER 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21 23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42 6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43 1, 29, 56 2, 27, 30, 55 28 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL An 1Bn 2Bn OEA, OE1B, OE2B LE1B, LE2B, LEA1B, LEA2B SEL GND VCC FUNCTION Data inputs/outputs (A) Data inputs/outputs (B1) Data inputs/outputs (B2) Output enable input (active low) Latch enable inputs B1/B2 input select input Ground (0V) Positive supply voltage
PIN CONFIGURATION
OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 1 2 3 4 5 6 7 8 9 56 OE2B 55 LEA2B 54 2B4 53 GND 52 2B5 51 2B6 50 VCC 49 2B7 48 2B8 47 2B9 46 GND 45 2B10 44 2B11 43 2B12 42 1B12 41 1B11 40 1B10 39 GND 38 1B9 37 1B8 36 1B7 35 VCC 34 1B6 33 1B5 32 GND 31 1B4 30 LEA1B 29 OE1B
FUNCTION TABLES B to A (OEB = H)
INPUTS 1B H L X X X X X 2B X X X H L X X SEL H H H L L L X LE1B H H L X X X X LE2B X X X H H L X OEA L L L L L L H OUTPUT A H L A0 H L A0 Z
A3 10 GND 11 A4 12 A5 13 A6 14 A7 15 A8 16 A9 17 GND 18 A10 19 A11 20 A12 21 VCC 22 1B1 23 1B2 24 GND 25 1B3 26 LE2B 27 SEL 28
A to B (OEA = H)
INPUTS A H L H L H L X X X X X LEA1B H H H H L L L X X X X LEA2B H H L L H H L X X X X OE1B L L L L L L L H L H L OE2B L L L L L L L H H L L OUTPUT 1B H L H L 1B0 1B0 1B0 Z Active Z Active 2B H L 2B0 2B0 H L 2B0 Z Z Active Active
SA00435
1998 Jan 30
3
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
LOGIC DIAGRAM (POSITIVE LOGIC)
LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL 2 27 30 55 56 29 1 28
C1 G1 A1 8 1 1 1D 23 1B1
C1
1D
6 2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
SA00436
1998 Jan 30
4
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output current Output in High state Storage temperature range -64 -65 to +150 C VI < 0 CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +7.0 -50 -0.5 to +7.0 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1kHz Input transition rise or fall rate; Outputs enabled Operating free-air temperature range -40 PARAMETER 2.5V RANGE LIMITS MIN 2.3 0 1.7 0.7 -8 8 24 10 +85 -40 MAX 2.7 5.5 3.3V RANGE LIMITS MIN 3.0 0 2.0 0.8 -32 32 64 10 +85 MAX 3.6 5.5 UNIT V V V V mA mA ns/V C
1998 Jan 30
5
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
74ALVT16260
LIMITS SYMBOL VIK VOH PARAMETER Input clamp voltage High-level out ut voltage output TEST CONDITIONS VCC = 3.0V; IIK = -18mA VCC = 3.0 to 3.6V; IOH = -100A VCC = 3.0V; IOH = -32mA VCC = 3.0V; IOL = 100A VOL Low-level out ut voltage output VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VRST Power-up output low voltage6 VCC = 3.6V; IO = 1mA; VI = VCC or GND VCC = 3.6V; VI = VCC or GND II In ut Input leakage current VCC = 0 or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0V IOFF IHOLD Off current Bus Hold current Data inputs7 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current Quiescent supply current Additional supply current per input pin2 VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VCC = 0V to 3.6V; VCC = 3.6V VO = 5.5V; VCC = 3.0V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don't care VCC = 3.6V; VO = 3.0V; VI = VIL or VIH VCC = 3.6V; VO = 0.5V; VI = VIL or VIH VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 75 -75 500 10 1 0.5 0.5 0.04 3.7 0.04 0.04 125 100 5 *5 0.1 6 0.1 0.4 mA mA A A A A Data pins4 ins Control pins 0.1 0.1 0.1 0.1 0.1 130 -140 A VCC-0.2 2.0 Temp = -40C to +85C MIN TYP1 -0.85 VCC 2.3 0.07 0.25 0.3 0.4 0.2 0.4 0.5 0.55 0.55 1 10 1 -5 100 A A V V MAX *1.2 V V UNIT
IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V 0.2V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Jan 30
6
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
AC ELECTRICAL CHARACTERISTICS (3.3V 0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500 SYMBOL FROM (INPUT) tPLH tPHL tPLH tPHL tPLH A or B PARAMETER TO (OUTPUT) B or A MIN 1 1 1.1 LE SEL (B1) SEL (B2) SEL (B1) tPHL tPZH tPZL tPHZ tPLZ SEL (B2) OE A or B A A A A A or B 1.1 1.3 1.1 1.5 1.6 1 1.6 2.2 OE A or B 1.3
74ALVT16260
Tamb = -40C to +85C VCC = +3.3V 0.3V TYP 2.8 2.6 2.9 3.1 2.3 2.4 2.4 2.4 2.3 2.3 4.4 3.1 MAX 4.8 4.6 4.6 4.7 3.4 3.8 3.6 3.6 4.2 4.0 6.0 5.0
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
AC SETUP CHARACTERISTICS (3.3V 0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500 SYMBOL tw tsu th PARAMETER Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high Setup time, data before LE1B, LE2B, LEA1B, or LEA2B Hold time, data after LE1B, LE2B, LEA1B, or LEA2B Tamb = -40C to +85C VCC = +3.3V 0.3V MIN 3.3 1 1 MAX ns ns ns UNIT
1998 Jan 30
7
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
74ALVT16260
LIMITS SYMBOL VIK VOH VOL VRST PARAMETER Input clamp voltage High-level out ut voltage output Low-level out ut voltage output Power-up output low voltage7 TEST CONDITIONS VCC = 2.3V; IIK = -18mA VCC = 2.3 to 3.6V; IOH = -100A VCC = 2.3V; IOH = -8mA VCC = 2.3V; IOL = 100A VCC = 2.3V; IOL = 24mA VCC = 2.7V; IO = 1mA; VI = VCC or GND VCC = 2.7V; VI = VCC or GND II In ut Input leakage current VCC = 0 or 2.7V; VI = 5.5V VCC = 2.7V; VI = VCC VCC = 2.7V; VI = 0 IOFF IHOLD IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Off current Bus Hold current Data inputs6 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current VCC = 0V; VI or VO = 0 to 4.5V VCC = 2.3V; VI = 0.7V VCC = 2.3V; VI = 1.7V VO = 5.5V; VCC = 2.3V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don't care VCC = 2.7V; VO = 2.3V; VI = VIL or VIH VCC = 2.7V; VO = 0.5V; VI = VIL or VIH VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = 05 VCC = 2.3V to 2.7V; One input at VCC-0.6V, Other inputs at VCC or GND Data pins4 ins Control pins 0.1 0.1 0.1 0.1 0.1 90 -10 10 1 0.5 0.5 0.04 2.7 0.04 0.04 125 100 5 -5 0.1 4.5 0.1 0.4 mA mA VCC-0.2 1.8 Temp = -40C to +85C MIN TYP1 -0.85 VCC 2.1 0.07 0.3 0.2 0.5 0.55 1 10 1 -5 "100 A A A A A A A V MAX -1.2 V V UNIT
NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V 0.3V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
1998 Jan 30
8
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
AC ELECTRICAL CHARACTERISTICS (2.5V 0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500 SYMBOL FROM (INPUT) tPLH tPHL tPLH tPHL tPLH A or B PARAMETER TO (OUTPUT) B or A MIN 1 1 1.1 LE SEL (B1) SEL (B2) SEL (B1) tPHL tPZH tPZL tPHZ tPLZ SEL (B2) OE A or B A A A A A or B 1.1 1.3 1.1 1.5 1.6 1 1.6 2.2 OE A or B 1.3
74ALVT16260
Tamb = -40C to +85C VCC = +2.5V 0.2V TYP 3.5 3.3 3.9 4.2 2.9 3.3 3.0 3.2 3.1 2.0 4.0 2.0 MAX 5.3 5.4 6.0 6.2 4.5 4.8 4.5 4.6 5.0 3.0 6.6 3.4
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
AC SETUP CHARACTERISTICS (2.5V 0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500 SYMBOL tw tsu th PARAMETER Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high Setup time, data before LE1B, LE2B, LEA1B, or LEA2B Hold time, data after LE1B, LE2B, LEA1B, or LEA2B Tamb = -40C to +85C VCC = +2.5V 0.2V MIN 3.3 1 1 MAX ns ns ns UNIT
1998 Jan 30
9
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
AC WAVEFORMS
VM = 1.5V for all waveforms The outputs are measured one at a time with one transition per measurement.
3V tw 3V INPUT VM VM 0V DATA INPUT VM VM 0V tsu th 3V TIMING INPUT VM 0V
SA00437
SA00439
Figure 1. Pulse duration
Figure 3. Setup and hold times
3V INPUT VM tPLH VM 0V tPHL VOH OUTPUT VM VM VOL tPHL tPLH VOH OUTPUT VM VM VOL OUTPUT WAVEFORM 2 S1 AT OPEN OUTPUT WAVEFORM 1 S1 AT 7V tPZH tPZL tPLZ OUTPUT CONTROL VM VM
3V
0V
3.5V VM tPHZ VOH VM VOH - 0.3V 0V VOL + 0.3V
VOL
SA00438
SA00440
All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, tr 2.5ns, tf 2.5ns. Figure 2. Propagation delay times; inverting and non-inverting outputs
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Figure 4. Enable and disable times; low- and high-level enabling
TEST LOAD CIRCUIT
7V 500 FROM OUTPUT UNDER TEST S1 OPEN GND
CL = 50pF (INCLUDES PROBE AND JIG CAPACITANCE)
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 7V Open
Load Circuit for Outputs Figure 5. Test load circuit
SA00441
1998 Jan 30
10
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1988 Jan 30
11
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1988 Jan 30
12
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
NOTES
1988 Jan 30
13
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03337
Philips Semiconductors
1988 Jan 30 14

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